Microchip Technology dsPIC33CK MC Digital Signal Controllers (DSCs)

Microchip Technology dsPIC33CK MC Digital Signal Controllers (DSCs) combine a high-performance 16-bit dsPIC33CK CPU with DSP capabilities, high-speed Pulse Width Modulation (PWM) peripherals, advanced analog features, and integrated communication interfaces. Operating at up to 100 MIPS, these DSCs are optimized for real-time control applications that require fast computation and precise signal processing. The dsPIC33CK MC family features high-resolution PWM generators, configurable 12-bit Analog-to-Digital Converters (ADCs), DMA channels, and CAN FD connectivity. These capabilities enable efficient control of DC/DC converters, AC/DC power supplies, power-factor correction stages, inverters, and intelligent lighting systems.

Designed for demanding motor control applications, the Microchip Technology devices support BLDC, PMSM, AC induction, stepper, and switched-reluctance motors. Integrated safety functions, diagnostic features, and industrial communication interfaces make the dsPIC33CK MC DSCs well-suited for industrial automation, robotics, automotive systems, and advanced embedded control platforms.

Features

  • Operating conditions
    • 3V to 36V range
    • DC to 100 MIPs range
    • -40°C to +125°C temperature range
  • 16-bit dsPIC33CK CPU core
    • 32Kbytes to 256Kbytes of program Flash with ECC and 8K to 16K data RAM
    • Fast 6-cycle divide
    • Code-efficient (C and assembly) architecture
    • 40-bit wide accumulators
    • Single-cycle (MAC/MPY) with dual data fetch
    • Single-cycle, mixed-sign MUL plus hardware divide
    • 32-bit multiply support
    • Five sets of interrupt context-selected registers for fast interrupt response
    • Zero-overhead looping
    • 384 bytes of One-Time-Programmable (OTP) memory
  • Clock management
    • Selectable oscillator options
      • 8MHz internal fast RC (FRC) oscillator
      • Primary high-speed, crystal/resonator oscillator or external clock
      • Primary PLL, which can be clocked from the FRC or crystal oscillator
    • Programmable PLLs and oscillator clock sources
    • Reference Clock Output (REFCLKO)
    • Fail-Safe Clock Monitor (FSCM)
    • Backup internal oscillator
  • Power management
    • Low-power management modes (Sleep, Idle, Doze)
    • Integrated power-on reset and brown-out reset
  • High-speed PWM
    • Four PWM pairs
    • Up to 2ns PWM resolution
    • Dead time for rising and falling edges
    • Dead-time compensation
    • Clock chopping for high-frequency operation
    • PWM support for
      • DC/DC, AC/DC, inverters, PFC, and lighting
      • BLDC, PMSM, ACIM, stepper motors, and SRM motors
    • Fault and current limit inputs
    • Flexible trigger configuration for ADC triggering
  • Timers/output compare/input capture
    • One general-purpose 16-bit timer
    • Peripheral Trigger Generator (PTG)
      • Up to 15 trigger sources to other peripheral modules
      • CPU-independent state machine-based instruction sequencer
      • Two 16-bit general-purpose timers
    • Four SCCP modules, which include timer, capture/compare, and PWM
      • Two 16-bit timers or one 32-bit timer in each module
      • PWM resolution down to 2.5ns (one output per SCCP module)
      • 16- or 32-bit capture
      • 4-deep capture buffer
    • Fully asynchronous operation, available in sleep modes
  • Advanced analog
    • High-speed 12-bit ADC
      • One shared SAR ADC core
      • Configurable resolution (up to 12-bit)
      • Up to 2Msps conversion rate per channel at 12-bit resolution
      • Up to 20 input channels
      • Dedicated result buffer for each analog channel
      • Flexible and independent ADC trigger sources
      • Four digital comparators
      • Four oversampling filters for increased resolution
    • One 30ns analog comparator
    • One 12-bit DAC with hardware slope compensation
  • Communication interfaces
    • Three protocol UARTs with automated protocol handling support for LIN 2.2, DMX, and IrDA®
    • Two four-wire SPI/I2S modules
      • 16-byte FIFO
      • Variable width
      • I2S mode
    • One CAN Flexible Data (FD) module
    • One I2C module with SMBus support
    • PPS to allow function remap
    • Programmable Cyclic Redundancy Check (CRC)
    • One SENT module
  • Four Direct Memory Access (DMA) channels
  • Peripherals
    • High-current I/O sink/source
    • Edge or level change notification interrupt on I/O pins
    • Peripheral Pin Select (PPS) remappable pins
  • Debugger development support
    • In-circuit and in-application programming
    • Three complex and five simple breakpoints
    • IEEE 1149.2 compatible (JTAG) boundary scan
    • Trace buffer and run-time watch
  • Safety
    • Backup Fast RC Oscillator (BFRC)
    • Brown-out Reset (BOR)
    • Capless internal voltage regulator
    • Clock monitor system with backup oscillator
    • CodeGuard™ security
    • Cyclic Redundancy Check (CRC)
    • Dual Watchdog Timer (WDT)
    • Fail-Safe Clock Monitoring (FSCM)
    • Flash Error Correcting Code (ECC)
    • Flash OTP by ICSP™ write inhibit
    • RAM memory Built-In Self-Test (MBIST)
    • Two-speed start-up
    • Virtual pins for redundancy and monitoring
    • Windowed Deadman Timer (DMT)
  • AEC-Q100 REV G qualified (Grade 1: -40°C to +125°C)

Applications

  • Industrial automation equipment
  • Factory motor drives
  • Robotics and motion control
  • Automotive control modules
  • Consumer appliances
  • Smart power management systems
  • Intelligent sensors and actuators
  • Embedded real-time control platforms
  • Renewable energy systems

Block Diagram

Block Diagram - Microchip Technology dsPIC33CK MC Digital Signal Controllers (DSCs)

CPU Block Diagram

Block Diagram - Microchip Technology dsPIC33CK MC Digital Signal Controllers (DSCs)
Publicado: 2026-10-19 | Actualizado: 2026-10-19